Field
The disclosed embodiments generally relate to clocked memory systems. More specifically, the disclosed embodiments relate to a memory system that uses asymmetric, source-synchronous clocking to facilitate changing a clock frequency without producing gaps in memory traffic.
Related Art
Memory systems in portable computing devices typically operate at reduced clock speeds when computational workloads are low. These reduced clock speeds enable the supply voltage to be reduced at the memory controller, which decreases power consumption and thereby extends battery life. However, dealing with these changing clock speeds can complicate the design of modern high-performance memory systems.
To increase bandwidth, memory systems can potentially distribute a reference clock and can perform rate multiplication to generate a higher frequency synchronized clock from the reference clock. This reference timing signal can potentially be multiplied using a conventional phase-locked loop (PLL) or a delay-locked loop (DLL). Unfortunately, PLLs and DLLs burn a significant amount of power, which makes them undesirable in portable computing devices, which have limited battery capacity. Moreover, when the reference clock frequency changes, the PLLs and DLLs need to be recalibrated, which can also impede system performance.
Hence, what is needed is a method and an apparatus for generating a multiplied timing signal without the above-described drawbacks of using a PLL or a DLL.